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jsspace 发表于 2016-10-11 11:34 
9 S: Y3 o/ y1 N( ^' i漏液不可以接受，不管是否灌胶。
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8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted to cool to8 t* ~ F6 g" r5 Y
room temperature and the dielectric voltage withstand test of 8.6 shall be repeated.
! W5 V& w2 N0 Q* t) j2 n8.7.1.3 A risk of fire or electric shock is considered to exist with any of the following results:
6 @; O0 l& m! H6 J; w. c7 da) Opening of the ground fuse,
& D# j! x3 j; O3 Xb) Charring of the cheesecloth or tissue paper,
[, o( U3 C v+ t1 e% Kc) Emission of flame or molten material from the unit,
; T. a ?6 t8 X! K4 Ud) Ignition or dripping of a compound from the unit,
# U( A( A5 S. le) Exposure of live parts that pose a risk of electric shock under the requirements for
^2 u9 p+ J( e+ y9 x) ?accessibility of 7.2, or; P: M6 C# @- m7 K" y' Q8 k8 {
f) Breakdown during the subsequent dielectric voltage withstand test.& T }5 k7 a9 v; @! d# V
Opening of the 20A time delay fuse is acceptable provided none of the other conditions noted in (a)) C* H9 t1 B2 d2 v$ ~' r2 w) }
through (f) occurs.0 h3 ~$ I7 H/ ~0 Q7 c8 d
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8.7.2 Component failure test( q- D$ @7 o( j$ j% |
8.7.2.1 A unit having components such as resistors, semiconductor devices, capacitors, and the like shall$ V0 w9 M' _$ I9 I3 z
not exhibit a risk of fire or electric shock when a simulated short circuit or open circuit is imposed. In
" Q" s* K# H/ @2 Z$ wpreparation for component failure tests, the equipment, circuit diagrams, and component specifications
* Z# g2 Y3 t* [: w; |3 T2 V" kare examined to determine those fault conditions that might reasonably be expected to occur. Examples' b0 \- C6 s5 K
include: short-circuits and open circuits of semiconductor devices and capacitors, faults causing open1 @/ X9 f3 Q3 P4 ~- A3 C" K1 ~
circuits of resistors and internal faults in integrated circuits.
9 ~% b# l# B% NException No. 1: Circuits in which maximum power levels have been determined to not exceed 50 W need% \' m2 A' g0 q, T" L
not be evaluated for component failure.8 }6 c6 [+ C }7 `3 c& o: u4 E- ~
Exception No. 2: Devices supplied by a source operating within the limits for risk of fire and electric shock ?% t* D+ J4 n; V% L- X2 j/ f
need not be subject to this test.. M% B; j; z( d% E
8.7.2.2 Each component is to be short circuited or open circuited, one at a time (one fault per test). Each* y4 D2 i& ~% ~8 b$ q7 U
test shall continue until either the unit is no longer operable, or until conditions are obviously stable (as2 E, d6 m- F& l% M7 y. j+ s+ D
determined by no visual.
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+ Q3 |# K2 A" y再核对一下标准看有没有答案？% b; w" b% _5 S* { i& @
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发表于 2016-10-11 11:21
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发表于 2016-10-11 12:39
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