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jsspace 发表于 2016-10-11 11:34  e/ i- f$ D/ N
漏液不可以接受，不管是否灌胶。
& A6 R; C* |+ B3 m1 Z/ d5 ^- I$ x8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted to cool to
5 g' `* q$ \+ yroom temperature and the dielectric voltage withstand test of 8.6 shall be repeated.& r3 S) u! Q& U6 t0 k
8.7.1.3 A risk of fire or electric shock is considered to exist with any of the following results:
1 F, q/ Z) X$ ha) Opening of the ground fuse,3 P& G* j. x' h2 Z
b) Charring of the cheesecloth or tissue paper,4 p2 Z' J' C# F5 r
c) Emission of flame or molten material from the unit,
. w7 a! {. f9 ld) Ignition or dripping of a compound from the unit,+ E: X8 U* o& s* d& R1 J
e) Exposure of live parts that pose a risk of electric shock under the requirements for
: D4 k$ ?% E; @* C1 S: qaccessibility of 7.2, or: U4 X/ Y, {0 ?# G. f2 e
f) Breakdown during the subsequent dielectric voltage withstand test.4 Y+ O# Z+ p) F2 W% H
Opening of the 20A time delay fuse is acceptable provided none of the other conditions noted in (a)7 k7 ~4 f: x8 C6 ~% d' y' ]. Y
through (f) occurs.! |5 S: b5 b) A; R1 V* v
k, H0 q: c# l8 F: v% C( V% f& W- c9 ^, i& {( J% X) `' x
6 V6 [$ d5 @( N F8.7.2 Component failure test% i h6 [6 T2 o& P1 f* g7 T
8.7.2.1 A unit having components such as resistors, semiconductor devices, capacitors, and the like shall
& Y: `8 n) k' p& L' snot exhibit a risk of fire or electric shock when a simulated short circuit or open circuit is imposed. In
! M! O9 e( p3 vpreparation for component failure tests, the equipment, circuit diagrams, and component specifications
8 S4 {- N3 \' u' P, l ^3 Nare examined to determine those fault conditions that might reasonably be expected to occur. Examples$ Z8 M( b+ S( t6 |
include: short-circuits and open circuits of semiconductor devices and capacitors, faults causing open' O" o; Y' n5 |1 ^4 N( |" N
circuits of resistors and internal faults in integrated circuits.
( G+ S) f; G# u% B3 j. bException No. 1: Circuits in which maximum power levels have been determined to not exceed 50 W need
& E- O$ w3 _, D; ?; knot be evaluated for component failure.
2 N1 ]4 [/ @5 }% e/ `3 ~Exception No. 2: Devices supplied by a source operating within the limits for risk of fire and electric shock i# e* ?' L7 u6 h$ r$ j0 C% z9 y
need not be subject to this test.
j6 I2 f2 ?1 v8 v0 Y8.7.2.2 Each component is to be short circuited or open circuited, one at a time (one fault per test). Each, k0 P: v: p* o6 w
test shall continue until either the unit is no longer operable, or until conditions are obviously stable (as
$ p( y) J2 }2 k' D. }2 Edetermined by no visual.
5 I( U: I7 N/ O$ A
' G$ q3 S/ J# Y; g( s N8 Q$ I9 H2 O# k# N. {3 B& C
再核对一下标准看有没有答案？
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发表于 2016-10-11 11:21
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发表于 2016-10-11 12:39
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