2 _& s7 v. S/ x4 m' e. G8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted to cool to % v7 [+ ]7 r' q. e: Q' }room temperature and the dielectric voltage withstand test of 8.6 shall be repeated.5 Q$ P3 o' t; V$ r1 F* u1 E
8.7.1.3 A risk of fire or electric shock is considered to exist with any of the following results: 9 g% Q, |6 t, D- f! {& L$ Fa) Opening of the ground fuse, 2 N `) t9 Y( nb) Charring of the cheesecloth or tissue paper, 7 {4 K& N N. u5 \3 ~c) Emission of flame or molten material from the unit, 1 t {/ g2 P2 D) L% A) v& P3 ad) Ignition or dripping of a compound from the unit,( P5 r* D% `4 p/ w
e) Exposure of live parts that pose a risk of electric shock under the requirements for, C7 ^% O$ p; {- k. _: f
accessibility of 7.2, or1 s: _+ }# Z% B5 C4 E, v0 O& o$ n
f) Breakdown during the subsequent dielectric voltage withstand test.7 l, h% Y3 q; |, c" B* v! i
Opening of the 20A time delay fuse is acceptable provided none of the other conditions noted in (a)5 H/ b* n& [- [2 a# A' O
through (f) occurs.) a& j6 F; z5 W% J& C0 A4 m
$ i1 `1 e/ q( _- n0 X1 I
9 B, A0 J& S C8 _ F1 w+ J: P) ] Y* [; k, J8.7.2 Component failure test ; B F- {2 q) ^# V E- b' C- m3 p: K; r8.7.2.1 A unit having components such as resistors, semiconductor devices, capacitors, and the like shall ) ]" ?& x$ b. d2 G# }* M8 @( Enot exhibit a risk of fire or electric shock when a simulated short circuit or open circuit is imposed. In " S2 ]7 `$ P9 e, Spreparation for component failure tests, the equipment, circuit diagrams, and component specifications- S* |) l) U( n1 |
are examined to determine those fault conditions that might reasonably be expected to occur. Examples 8 y! g7 r# m5 f! ?( Ninclude: short-circuits and open circuits of semiconductor devices and capacitors, faults causing open 2 v5 v" H# r" d7 z6 T* q8 }circuits of resistors and internal faults in integrated circuits.: X3 p5 n* ?. s1 o# W: q
Exception No. 1: Circuits in which maximum power levels have been determined to not exceed 50 W need1 \9 [5 U+ c3 D; ?4 j
not be evaluated for component failure. , z" }/ e# [$ E1 s: [. p; {Exception No. 2: Devices supplied by a source operating within the limits for risk of fire and electric shock 3 g0 [+ p- L9 G- d- @need not be subject to this test. " q3 e# J4 X5 U8 U; ~8 U9 G8.7.2.2 Each component is to be short circuited or open circuited, one at a time (one fault per test). Each- s1 m1 c* j# H) F: q2 J% ^5 U
test shall continue until either the unit is no longer operable, or until conditions are obviously stable (as& p) x4 S, c& h! J& d- o# |3 d3 ]( e
determined by no visual. % c! I* W( O' }/ z) M* j- N4 u7 V7 w4 c) \, W